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July 20th, 2011

Get flexible: Georgia Tech group shows how to ‘draw’ nano-sized ferroelectric structures on plastic substrates

Published on July 20th, 2011 | By: pwray@ceramics.org

Georgia Tech researchers display samples of materials on which ferroelectric nanostructures have been fabricated by thermochemical nanolithography. Graduate research assistant Yaser Bastani (left) with silicon, assistant professor Nazanin Bassiri-Gharb with polyimide and postdoctoral fellow Suenne Kim with glass. (Credit: Gary Meek, Georgia Tech.)

“We can directly create piezoelectric materials of the shape we want, where we want them, on flexible substrates,” says Nazanin Bassiri-Gharb in a Georgia Tech press release. “This is the first time that structures like these have been directly grown with a CMOS-compatible process at such a small resolution. Not only have we been able to grow these ferroelectric structures at low substrate temperatures, but we have also been able to pattern them at very small scales.”

Bassiri-Gharb, a mechanical engineering assistant professor at the Georgia Institute of Technology, and others at the school have been learning how to successfully use thermochemical nanolithography to make nanometer-scale ferroelectric structures directly on bendable plastic substrates. From an applications viewpoint, this means manufacturers can now use TCNL on a substrate that would typically be ruled out because it would be unable to withstand normal processing temperatures.

The TCNL efforts are described in recent paper in Advanced Materials (doi:10.1002/adma.201101991).

TCNL, itself, isn’t novel and apparently was developed around 2007 at Georgia Tech. In general, it involves the use of a heated atomic force microscope tip to produce patterns. Since then, investigators have been perfecting where its use might be most beneficial.  Because the polarization of ferroelectrics can easily be toggled they are of interest for random access memory elements.

In this new paper, investigators report they have produced wires approximately 30 nanometers wide and spheres with diameters of approximately 10 nanometers using the patterning technique. According to Suenne Kim, the paper’s first author and a postdoctoral fellow in GT’s School of Physics, “Spheres with potential application as ferroelectric memory were fabricated at densities exceeding 200 gigabytes per square inch, currently the record for this perovskite-type ferroelectric material.”

According to a GT news release, the group hopes their work demonstrates how TCNL could lead to high-density, low-cost production of complex ferroelectric structures. The types of applications they have in mind are energy-harvesting arrays, sensors and actuators in nanoelectromechanical systems and microelectromechanical systems.

Image shows the topography (by atomic force microscope) of a ferroelectric PTO line array crystallized on a 360-nanometer thick precursor film on polyimide. Bar corresponds to one micron. (Credit: Suenne Kim, Georgia Tech.)

The problem is that normal ferroelectric crystallization processes require temperatures that exceed 600°C. Typically, ferroelectric structures first had to be grown on a single-crystal substrate and then transferred to a flexible substrate for use in energy-harvesting. But, by using an AFM tip on amophous precursor materials, TCNL leads to only “extremely localized heating” that is more on the order of 250°C, Then, it’s only a matter of matter of using computer controls to draw patterns of crystallized material, for example, lines of ferroelectric nanowires drawn along the direction in which strain would be applied.

The GT group says it has created lead titanate and lead zirconate titanate structures on polyimide, glass and silicon substrates. In general, however, the researchers say the only substrate requirement is that it be able to withstand the 250” heating step.

Next, the group says it plans on assembling arrays of AFM tips to produce larger patterned areas, and also get a handle on the growth thermodynamics of ferroelectric materials at the nanoscale.

Pztlines-sem: Scanning electron microscope image shows a large PZT line array crystallized on a 240-nanometer thick precursor film on a platinized silicon wafer. (Credit: Yaser Bastani, Georgia Tech)

Pztlines-sem: Scanning electron microscope image shows a large PZT line array crystallized on a 240-nanometer thick precursor film on a platinized silicon wafer. (Credit: Yaser Bastani, Georgia Tech.)

“We are really addressing the problem caused by the existing limitations of photolithography at these size scales,” says GT physics professor Elisa Riedo, in the news release. “We can envision creating a full device based on the same fabrication technique without the requirements of costly clean rooms and vacuum-based equipment. We are moving toward a process in which multiple steps are done using the same tool to pattern at the small scale.”

The research was sponsored by NSF and the DOE, and also involved scientists from the University of Illinois Urbana-Champaign and the University of Nebraska Lincoln.

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